I’ve posted in a previous post that I implemented a clock in the atmel, and that there is an offset because of the time it takes between the calling of the signal, and me setting the counter back to 0.
This wasn’t true,Â I run the counter with a prescaler of 1/256. So the value of the clock is incremented every 256 cycles. So between calling the signal, and setting it to 0, I have more then sufficient clock cycles. I just have todo it within 256 cycles. One problem solved or not?
In the documentation it’s not 100% clear if the signal is directly called when the counter matches, or one counter cycle (so 256 clock cycle later).Â I have to look into this, but solving this misunderstanding did give me a way to correctly backtrace what it does.